The study by Fraunhofer AISEC on the security of cryptographic hardware implementations focuses on attacks on physical hardware, such as side-channel attacks and error attacks, as well as measures to defend against them. These protective mechanisms can potentially be compromised by optimizations in the chip design process. The study shows that protective measures should be integrated into complex design processes and taken into account in hardware design synthesis in order to be resilient to hardware attacks. The findings will help hardware designers to develop robust and secure chips.